Listening to the radio with ADC and FPGA had been on my to-do list for quite some time before I discovered Red Pitaya. At that time, it was the first board that provided the exact combination of features that I was looking for, and more. I was very surprised to find out that there was no open-source Software Defined Radio (SDR) project based on Red Pitaya. So, I decided to create such a project. This was in December 2014.
The initial objectives of my SDR project could be summarised in the following points:
• get familiar with new Xilinx chips and tools,
• keep the number of lines of code low,
• make use of the existing libraries and programs.
After less than one year, in September 2015, I released the first version of the dual channel SDR transceiver that can now be used with several SDR programs and frameworks: HDSDR, Gqrx, GNU Radio, GNU Radio Companion and Pothos. Shortly after, there also appeared a version compatible with the software developed by the HPSDR project and other SDR programs supporting the HPSDR/Metis communication protocol: PowerSDR mRX PS, Quisk, ghpsdr3-alex, openHPSDR Android Application, Ham VNA, etc. Both versions of the SDR transceiver applications are available from the Red Pitaya application marketplace.
When started, the SDR transceiver applications configure the FPGA and start TCP or UDP servers that communicate with SDR programs running on a remote PC.
The main blocks of the FPGA configurations are interfaces with ADC and DAC, digital down- and up-converters, FIFO buffers, configuration and status registers.
The digital down- and up-converters consist of the following blocks:
• direct digital synthesizer (DDS) generating a complex sinusoid,
• complex multiplier,
• CIC filter that is used to decrease the sample rate by a configurable factor,
• FIR filter that compensates for the drop in the CIC frequency response and reduces the sample rate by a factor of two.
The basic blocks of the digital down-converter are shown on the following diagram:
The digital up-converter consists of similar blocks but arranged in an opposite order:
Only a few custom IP cores had to be written for the FPGA configuration, thanks to the rich library of IP cores coming with Xilinx Vivado Design Suite.
The job of the TCP and UDP servers running on the on-board CPU is to transmit/receive data to/from SDR programs running on a remote PC. The servers communicate with the FPGA configuration via FIFO buffers, configuration and status registers.
The SDR programs provide graphical user interface, spectrum display, modulation/demodulation and any other functionality useful for radio applications.
For those interested in reading more about Digital Signal Processing (DSP) and Software Defined Radio (SDR), I can recommend the following on-line resources:
• The Scientist and Engineer’s Guide to Digital Signal Processing by Steven W. Smith
• dspGuru: Digital Signal Processing Articles
• ARRL: Software Defined Radio
• GNU Radio: Suggested Reading
The most popular application seems to be the SDR transceiver compatible with HPSDR used together with PowerSDR mRX PS. I am glad to find that radio amateurs interested in my SDR projects share the results of their tests.
Wolfgang Kiefer (DH1AKF) published pictures of his 5W station.
Ger Metselaar (PAØAER) compared Red Pitaya SDR with Flex-6500 and Red Pitaya SDR performed quite well, taking into account the 10 fold difference in price.
Johan van Dijk (PA3ANG) published an article about Red Pitaya SDR in the January, 2016 issue of DKARS Magazine.
Red Pitaya is a very interesting platform for experimenting with FPGA and DSP algorithms and sharing knowledge and experiences. It is also a nice SDR building block, thanks to the excellent open-source SDR tools.
The source code and more information about my projects based on Red Pitaya can be found here.
I’ve recently spoken about my SDR projects at the FOSDEM free/open source software conference. The slides of my talk can be found here.
Who is Pavel Demin?
Pavel Demin is a particle physicist and IT engineer fascinated by everything programmable. He works at Université catholique de Louvain in Belgium and plays with micro-controllers and FPGAs in his spare time.